EE 272 - SoC Design & Verifi. with System Verilog

3 unit(s)
The course covers topics in System-on-Chip design and verification with SystemVerilog. Major topics include top-down SoC design; design metrics, techniques, and system-level synthesis; IP integration and system-level verification; SystemVerilog design hierarchy, data types, assertions, interfaces, verification constructs, and testbench structures.

Prerequisite(s): EE 271 or instructor consent.
Grading: Letter Graded

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