EE 273 - Logic Verification with UVM

3 unit(s)
Covers non-design System Verilog and Universal Verification Methodology (UVM). It introduces logic verification methodologies and techniques. No prior object oriented programming is assumed. UVM is practiced on sample designs in lab projects with industrial simulation tools.

Prerequisite(s): EE 271 or instructor consent.
Grading: Letter Graded

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